1. Field of the Invention
The present invention relates generally to a method for manufacturing a damascene structure, and more particularly, to a method for manufacturing a damascene structure capable of improving chemical mechanical polishing (hereinafter abbreviated as CMP) result.
2. Description of the Prior Art
In the fabrication of semiconductor integrated circuits (ICs), semiconductor devices are generally connected by several metallic interconnecting layers commonly referred to as multi-level interconnects, and damascene process has been deemed a convenient and predominant method for forming the multi-level interconnects. Principally, the damascene process includes etching a dielectric material layer to form trench and/or via patterns, filling the patterns with conductive materials such as copper, and performing a planarization process. Thus a metal interconnect is obtained.
Those skilled in the art have well known that the topography and pattern densities of the surface being polished influence the CMP result greatly. For example, when a surface being polished includes patterns having different pattern densities, the planarization rates of the CMP are different based upon respective pattern densities, and thus evenness of the planarized surface is inferior, and even suffers dishing problem.
Since the CMP process is one accepted method of planarization and now typically employed in the industry, it is always in need to solve the inferior evenness and dishing problem that are caused by different pattern densities.